1. Field of Invention
This invention relates to the field of bubble (magnetic domain) memories and in particular to the most efficient configuration of such memories to enable mass production thereof.
2. Prior Art
In order to make large mass memories of the bubble domain type practical, it must not only be compatible with other computer systems but also it must have mass production capabilities. This invention teaches how both of these goals can be realized.
As to the mass production capabilities in the manufacture of bubble memories, chips are formed on a large wafer containing a greater number of such chips, each of which contains a permalloy overlay pattern of magnetic elements which, together with the garnet bubble supporting film, provides means for propagating bubbles through the memory in response to a rotating in-plane magnetic field. Several forms of propagate elements together with bubble generators, replicators, annihilators, magnetoresistive detectors, etc., are now well known in the art. Also, one of the most popular organizations of these memories is a cluster of many storage loops served by one input and one output track. This not only improves access time but also makes redundant loops possible. The use of this redundancy will be clear hereinafter.
When such chips are formed on a wafer, usually by a photolithographic process with masks to define the configuration, for any number of reasons, one or more of the storage loops on a chip may be found to be defective. This means the defective storage loop is incapable of supporting one or more of the bubbles under the propagate elements; or stated another way, a number of bit positions on the storage loop is lost. This fault would introduce, of course, error into the memory and ordinarily would be a reason for rejecting an entire chip or perhaps a number of chips on a wafer. This large reject rate, of course, increases the cost of manufacture of chips.
There are a number of schemes, both in the patented art and in the literature, directed to solutions to this problem, i.e., means to tolerate defective loops on the chips and thus improve yield and reduce cost. Typical examples are the U.S. Pat. No. 3,909,810 to Naden, et al, and the article by the same inventor entitled, "Fault-Tolerant Memory Organization", appearing in the IEEE Journal Transactions on Magnetics, Vol. Mag-10 of September 1974, page 852, et seq.; the U.S. Pat. Nos. 4,001,673 to Barrett, et al; 3,990,058 to Archer, et al; 3,921,156 to Yoshimi; and 3,792,450 to Boger, et al.
The U.S. Pat. No. 3,909,810 to Naden, et al, shows a scheme in which a flag chip is utilized to prevent faulty loops on the data chips from being used for data storage but, on the other hand, this flag chip itself is used to store the data that would otherwise have been entered into the defective storage loop. This flag chip has a plurality of storage loops corresponding in number to the number of storage loops in the data chip and also uses a major loop for transferring data in and out of the loops of the flag chip. Thus, it, too, is subject to the same defect problem as the data chip since it, too, must be a perfect chip and is expensive for that reason. Also, in the organization therein disclosed, there is a time delay in getting the bubbles out of the flag chip which slows the overall system access time.
It is therefore an object of this invention to provide a defect tolerant memory organization which is simpler than the prior art organization and is thus less expensive and less subject to having defect problems.